1. Field of the Invention
The present invention relates to a semiconductor memory device wherein a first source voltage corresponding to a power source voltage is supplied to a semiconductor memory chip when data is written or read by an external device, and a second source voltage lower than the first source voltage is supplied to the chip when data is not read or written for a long period of time, i.e., when the chip is in a data maintaining state, in order to reduce overall power consumption.
2. Description of the Related Art
In recent years, there has been growing demand for a semiconductor memory device (hereinafter referred to as a semiconductor memory) which can be driven at higher speed yet consumes less power. A semiconductor memory with lower power consumption is in particularly great demand, since this would reduce the amount of heat generated in a system including a semiconductor memory. A system such as a large-size computer, which includes a number of semiconductor memories, may malfunction due to the amount of heat generated within itself, or a large cooling device must be provided to prevent heat from generating.
Low power consumption is particularly attractive where the semiconductor memory is used in a portable battery-driven personal computer, to increase the lifetime of the battery as long as possible.
To date, various attempts to reduce the power consumption of a semiconductor memory have been made. For example, a static random access memory (SRAM) or pseudo-static random access memory (PSRAM) can lower the source voltage under the control of an external device such as a computer, when data is not accessed, i.e., during a data maintaining period. The lowered source voltage is supplied to an internal circuit of a semiconductor chip to reduce power consumption. This is called a BBU mode (battery back-up mode).
In a dynamic random access memory (DRAM), power consumption is suppressed by increasing the period of time during which memory cells are refreshed.
However, it is difficult for a system including a SRAM or a PSRAM to control the source voltage in accordance with the state of the internal circuit of a semiconductor chip, i.e., depending on whether the internal circuit is in a stand-by state or operating.
Alternatively, the SRAM can decrease the power consumption in response to a chip select signal when the chip is in a stand-by state. However, since, in this case, an operation begins in a state where the source voltage is low, the memory cannot be accessed at high speed.
While the power consumption of a DRAM can be decreased by increasing the refresh time, increasing of the refresh time is limited since pause characteristics must be taken into account.
As described above, in the case where a method for lowering the source voltage in an access stand-by state is employed to decrease power consumption, it is difficult for a control system to control the source voltage outside the semiconductor chip. On the other hand, in order to increase the lifetime of the semiconductor chip, when a method for lowering the source voltage inside the semiconductor chip and supplying it to an internal circuit is employed, the lowered source voltage is generally applied also to peripheral circuits in a stand-by state. Therefore, since an access operation always begins in a state wherein the source voltage is low, the memory cannot be accessed at a high speed. Thus, the conventional semiconductor memory device cannot simultaneously achieve high-speed operation and low power consumption.